This invention relates generally to printed circuit board manufacturing and more specifically to a method of designing and testing printed circuit boards.
Printed circuit boards (PCB) are flat boards that electrically connect different components of a circuit through copper tracks called traces. Today, PCB""s are ubiquitous. They can be found in personal computers, cell phones, personal data assistants (PDAs) and so on.
Any printed circuit board (PCB) that contains a number of components (memory chips, processors, I/O chips, and other logic chips) must be designed with debugging in mind. A computer-aided design (CAD) tool is usually employed to xe2x80x9clayoutxe2x80x9d the chips on the board and then to perform xe2x80x9croutingxe2x80x9d of signal lines (called xe2x80x9ctracesxe2x80x9d) on the board. The board may be designed with multiple layers in order to accommodate the large number of traces in the design. To support debugging, printed circuit boards are often designed with debug or monitor connectors included on the board that provide connections to various critical traces on the board. A prototype board can then be tested with, for example, a logic analyzer, by connecting the probes of the analyzer to the debug connectors. After the debug phase is complete, the debug connectors are removed from the design, and the board is xe2x80x9cre-routedxe2x80x9d without them.
There are two problems with this approach. First, it takes time to completely re-route the board after the debug phase. Second, the re-routed board is physically, and thus electrically, different than the original debug version. This can change the electrical characteristics of the board. Consequently, the re-routing step may introduce new errors that will not be caught.
For the foregoing reasons, there is a need for a printed circuit board design methodology that permits effective debugging but that does not require a complete re-routing of the board design after the debug phase. The present invention satisfies this need.
The present invention is directed to a method and apparatus for designing a printed circuit board that reduces debugging time by not requiring the board to be re-routed after debugging. By reducing the debugging time, the manufacturer can release the product to market faster.
According to the present invention a computer-aided design (CAD) tool is used to create a preliminary design of a multi-layered printed circuit board. The design comprises a layout of the electrical components on a main region of the printed circuit board and a routing of signal traces among the electrical components within the main region. The signal traces are disposed on one or more signal layers of the printed circuit board.
An extended region is then added to the design in the CAD tool without disturbing the original traces on the main region of the printed circuit board. The extended region comprises a layout of selected debug connectors and at least one additional signal layer. Traces connecting the debug connectors to selected vias of the main region of the printed circuit board are then routed on the added signal layer.
A printed circuit board prototype is then manufactured from the design and includes both the extended region and the main region. This board can then be tested using the debug connectors, as needed, to monitor selected signals on the main region of the board.
Once testing is complete, the extended region and the at least one additional layer are removed from the design in the CAD tool without disturbing the layout of components and routing of signal traces on the main region of the printed circuit board. Unlike prior design methods, there is no need to reroute the signal traces of the main region after removal of the extended region. This reduces the chances that new errors will be introduced into the design of the main region.
The advantages of the invention combined with other attributes thereof will become more apparent upon consideration of the ensuing specification, particularly when considered in light of the attached drawings, directed towards particular embodiments of the invention but also illustrative of the underlying concepts thereof.